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Microchip Technology /ATSAME51J19A /CAN0 /TEST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LBCK)LBCK 0 (CORE)TX0 (RX)RX

TX=CORE

Description

Test

Fields

LBCK

Loop Back Mode
TX

Control of Transmit Pin

0 (CORE): TX controlled by CAN core

1 (SAMPLE): TX monitoring sample point

2 (DOMINANT): Dominant (0) level at pin CAN_TX

3 (RECESSIVE): Recessive (1) level at pin CAN_TX
RX

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Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data